CMOS image sensor arrays can employ several types of pixels. Passive pixel sensor cells are comprised of a simple photodiode and an access transistor. Active pixel sensor (APS) cells have added features including a reset transistor and a source follower amplifier.
A conventional APS sensing array is composed of individual light sensitive transducers called pixels that are organized in rows and columns. One typical pixel arrangement is composed of a photodiode (with junction capacitance), a reset transistor with a reset gate, an amplifier transistor, and a row select transistor.
During the reset cycle, charge is transferred onto the capacitive element through the reset transistor. An integration cycle allows charge from the capacitive element to be discharged through the photodiode. The remaining charge is then sampled by the amplifying gate and transferred to column amplifiers through the row select transistor. Upon completion of this cycle, the capacitive element in the array must be reset via the reset transistor. At this moment, a substantial amount of charge can be driven onto the substrate, raising the substrate bias voltage. Since the substrate is common for both the sensor array and peripheral circuitry, a significant increase in substrate charge increases the substrate bias voltage, which in turn can cause a circuit malfunction referred to as latch-up.
Latch-up is defined as the generation of a low-impedance path in CMOS devices between the power supply rail and the ground rail. It is a well known fact that, under certain conditions, a parasitic PNPN junction can be created in a CMOS integrated circuit, resulting in the latch-up and possibly destruction of the CMOS integrated circuit.
Latch-up is a parasitic conduction mechanism to which CMOS structures have an inherent vulnerability. It is a thyristor operating mechanism that can be triggered in PNPN structures. If any such PNPN structure is triggered into latch-up on a chip, large currents can flow and the results are usually irreversibly catastrophic for the entire chip.
Traditionally, integrated circuit designers have often relied on the fact that, typically, the operating characteristics of a CMOS integrated circuit are insufficient to surpass the high current threshold for triggering a latch-up. The potential problem is evaded by placing many substrate connections around the circuit. The substrate connections can draw off any potential current overload and prevent the latch-up triggering. However, in imaging circuitry, the fill factor, or percentage of the total pixel real estate that is effectively photosensitive, is significantly reduced if substrate connections were to be integrated within the cell. It is therefore impractical to place substrate connections within the array. In conventional APS imaging arrays the array size and the amount of charge being discharged upon reset is insufficient to cause latch-up, but due to the increasing size of sensor arrays, (1.3 Mpixels), the charge increase must be considered.
Several methods are used to prevent circuit latch-up, including well definition and the reduction of the lateral resistance of the n-tub. Well definition can effectively prevent PNPN junction formation particularly for small circuits; however, the amount of charge related to an array reset can be too great for sufficient latch-up prevention using the well definition method. Since the presence of large lateral resistance in the n-tubs has been found to cause latch-up, it was felt that the reduction of lateral resistance may prevent latch-up. Although this method is proven to be effective, it cannot handle large currents. Additionally, a change in the process for semiconductor substrates also increases costs, which should be minimized for production.
U.S. Pat. No. 5,881,184 which was issued on Mar. 9, 1999, describes a pixel for an imager in which the reset transistor either has two functions or is replaced by two reset transistors. In the latter case, the only way that the pixel can be reset is if a reset signal is applied to the gates of both of the transistors. The advantage of this is that each pixel can be reset individually rather then having all of the pixels in a row reset at the same time. This reference does not address the problem of the occurrence of latch-up during pixel resetting.
Therefore, there is a need for a method and apparatus for safely resetting active pixel sensor arrays without a significant increase in current that may cause destructive latch-up.